Modern-day semiconductor devices, commonly called integrated circuits, are fabricated on semiconductor wafers, and the wafers are then diced into grids, separating the integrated circuits into individual dies prior to final assembly. Integrated circuits are typically constructed at the surface of a wafer sliced from a single-crystal silicon ingot, although other semiconductors such as gallium arsenide and germanium are also used. Individual circuit elements, which form integrated circuits, are fabricated on and into the wafer surface, or substrate.
The electrical conduction between appropriate circuit elements, and required electrical isolation between other circuit elements, is then established using alternating layers of appropriately patterned conductors and insulators. Substantially vertical, conductive tunnels called “vias” pass through insulating layers as needed to form conductive pathways between adjacent conductive layers. The creation of circuit elements and their interconnections involves a complex series of fabrication steps including ion implantation, thin film deposition, photolithography, selective etching, diffusion and various cleaning processes.
The surface area required by a given integrated circuit is a function of both the complexity of the design (i.e., the number and arrangement of individual transistors, capacitors, resistors and other electronic circuit elements) and the dimensions of each circuit element. In general, the footprint of individual dies is much smaller than the surface area of the wafer. Consequently, a single wafer can generally yield multiple—often even thousands of—integrated circuits. When patterned on a wafer or subsequent to singulation, integrated circuits are commonly referred to as “dies,” a term which often refers more to the entire physical entity, including the substrate and all circuitry patterned thereon, rather than simply the circuitry.
Rectangularly shaped dies are generally arranged as closely as is feasible in a rectangular array on the wafer surface. Because of the resemblance to city maps, the spaces between dies are commonly termed “scribe streets.” The scribe streets are sacrificial areas reserved for singulating the wafer into dies. Cost-effective silicon substrate use and wafer-level processing require that a single wafer yield as many usable integrated circuits as possible, which requires—among other things—minimizing the damage to the dies incurred by sawing through the scribe streets. Accordingly, several parameters are managed during singulation processes to ensure a precise cut.
The arrangement of dies on the wafer surface and the corresponding scribe streets are depicted in FIG. 1. The single-crystal wafers 10 used in semiconductor processing are generally circular, and often have an edge notch 12 that allows proper orientation of the wafer during alignment-critical fabrication and singulation processes. Older or smaller wafers may utilize a “major flat,” or flat edge (not shown) instead of a notch. The integrated circuits 14 constructed on the wafer 10 are separated from one another by the grid formed by scribe streets 16. As is evident from FIG. 1, usable wafer surface area is limited both by the number and width of the scribe streets and by the circular shape at the periphery of the wafer that results in partial, non-functional devices 18. To conserve valuable usable wafer surface area, scribe streets are generally designed as narrow as possible, while still leaving adequate tolerances for the singulation process, so that rough or damaged areas do not affect active areas of the adjacent dies.
Mechanical saw singulation provides a number of advantages and is the most common die singulation process. Saw singulation allows quick, precise and accurate control over cut location and depth. Consequently, saw singulation can be used to cut either partially or completely through a wafer. Saw singulation operations typically utilize specially designed rotary dicing blades that can slice through the wafer substrate along the scribe streets defined by the individual dies. While often referred to as “sawing,” saw singulation generally uses an abrading process, wherein a circular blade composed of abrasive materials embedded in a binder matrix rotates at high speeds to grind away the wafer material.
FIGS. 2a and 2b show a typical dicing wheel 20 in profile and side views, respectively, for making high-precision cuts of semiconductor wafers. The dicing wheel 20 is typically part of a larger apparatus that receives material on a flat “table” surface 22 and traverses the material with the dicing wheel on command or at regular intervals. The dicing wheel 20 of FIG. 2 is secured on a shaft 24 by a nut 26. A blade 28 is held between two portions of a hub 30. The entire assembly typically rotates between 25,000 and 45,000 rpm during singulation.
The dicing blade commonly consists of diamond grit embedded in a thin aluminum matrix, although other suitable blade materials exist. The blade thickness can vary, but typically is between 15 and 140 microns (μm). The diameter can vary similarly, but typically is between about 5 and 10 centimeters (cm). The hub diameter is typically about ninety-eight percent of the blade diameter. Thus, in a typical arrangement, only the outer 125 to 1250 μm of the blade is exposed. This is necessary to provide adequate tensile strength and rigidity for the blade. Control over the width of the cut, or kerf, through the wafer can be obtained by proper blade selection; thinner blades provide a smaller kerf, helpful when used with narrower scribe streets.
FIG. 3 shows a magnified, cross-sectional view of a wafer 10 being cut by a saw blade 28. An adhesive tape backing 32 mounted on a circular frame (not shown) is usually attached to the wafer 10 to hold the dies in place during the singulation process. The blade 28 typically creates a cut slightly wider than the thickness of the blade, but narrower than the scribe street through which it passes. As mentioned previously, blade 28 may cut only partially through a wafer 10, but typically cuts through the entire thickness of the wafer, slightly scoring the adhesive 32 in the process. Alternatively, a series of dicing blades with different thicknesses may be used, with a first blade cutting the wafer to a first depth, and a second, generally thinner blade passing through the cut to completely saw through the wafer.
Currently, prior to singulation, wafers may undergo backgrind and polishing operations, abrasive processes intended to reduce the thickness of the wafer to a desired value and ensure global planarity, and to smooth the backside surface of the wafer to reduce roughness, respectively. Achieving a planar and smooth wafer backside is important for many reasons, but it has been discovered that surface roughness can contribute to greater material stresses on singulation, and consequently to cracking and related “chipping” of the sawn edges. In a typical singulation process, wafers are typically singulated with the dicing blade first impacting the top, active surface of the wafer, slicing through the bulk of the wafer, and finally cutting through the backside of the wafer.
Stress risers generally originate from relatively sharp angles or other discontinuities on the material surface, and may initiate local cracking and/or chipping when contacted with the dicing blade. A stress riser is a notch or other non-planar discontinuity in a material that may be a starting ingredient for a crack or tear. Silicon is a particularly brittle material that is especially susceptible to the propagation of cracks.
In the area of a stress riser, the cohesive strength of the material may be exceeded under pressure from the dicing saw, and the material may fracture, most likely in a crevice between two irregularities. If no flaw were present, under a similar load, the fracture strength would be equal to the cohesive strength of the material—i.e. greater stress would be required to fracture the material. As the saw slices through the wafer down towards the wafer backside, the stresses created propagate through the wafer material and may then lead to even greater chipping on the backside. As the wafer backside is under a tensile stress during this process, due to the greater outward forces pulling the material apart, cracking or chipping on this bottom surface may be more severe that that on the active surface, which would generally be under a compressive stress in the area of the saw blade.
Greater material chipping is generally seen on surfaces opposite the surface first contacted by the blade. It will be understood that, while the singulation processes shown describe a wafer being sawn from the active surface down, this arrangement may vary depending on process setup. However, if one of the surfaces is treated to increase planarity, due to the reduction of stress risers and propagation of stresses throughout the material, both top and bottom surfaces may experience reduced cracking and chipping as a result.
As shown in a perspective view of a die backside in FIG. 4, dies 10 are prone to chipping during singulation. Chipping occurs when fragment-like voids 40, or areas where material has cracked then chipped off, are created on die corners formed by the top surface (not shown) and a side 44 of the die, and the bottom surface 46 and a side 44 of the die. It will be understood that material voids 40 caused by chipping exist in several shapes and sizes along the sawn edges, but generally result in shards of material being removed. During singulation, shard-like remnants may be deposited on the active surface of the wafer, an area particularly sensitive to debris and other particles. Due to the possibility of particulate contamination and of cracking and chipping damaging nearby circuitry structures, it is important to reduce this occurrence as much as possible.
Often, after saw singulation, dies are lifted from the adhesive backing with a “pick and place” apparatus, which places each die on a package leadframe or substrate. The leadframe or substrate is then electrically interconnected to the die using wire bonding or other bonding process. However, a growing trend is for semiconductor suppliers to provide their customers with unpackaged dies, which may be designed for direct attachment to a motherboard, such as with a C4 bump attach process, or alternatively, designed for later packaging by the customer. While packaged dies would obscure any visual evidence of die edge cracking or chipping, unpackaged dies do not. The presence of cracking and chipping is not only cosmetic; cracking and chipping on the die edges can propagate stresses through the die material, potentially damaging the active circuitry and impairing functionality of the die, which can lead to customer returns of the defective product and lost revenues. Consequently, reducing the die edge damage incurred by singulation is of growing concern.
Several parameters can be adjusted to improve the quality of wafer singulation and to reduce cracking and chipping. Increasing the rotational speed of the blade may lessen damage to the wafer, as may reducing the linear speed (or feed) of the blade relative to the wafer. Selecting a dicing blade having a different size or shape of particles, as well as a different profile shape (such as square versus rounded) may produce a different cut quality. Similarly, selecting a blade with a different thickness may vary kerf width, while selecting a blade with a larger diameter may reduce surface contact forces, since the contact angle is likely to be smaller. Other process variations used to control cut quality include using multiple passes of a single blade, following a thicker blade with a thinner blade, or reversing blade rotation relative to feed direction. In addition, replacing the dicing blade more frequently may assist in lowering damage done to the wafer during singulation, while selecting a tackier adhesive backing may provide a greater resistance to tensile stresses on the constrained side, potentially reducing cracking and chipping.
Acceptable cuts can be made by adjusting one or more of the aforementioned parameters, but these parameters must be closely monitored to produce adequate results. Slight process variations can inadvertently produce unacceptable singulation results. What is needed is a process by which the wafer surface can be treated prior to singulation, smoothing the surface to reduce the occurrence of cracking and chipping within a wider range of process settings, and also to reduce the number of semiconductor rejects or customer returns related to material fractures and stress-induced damage. As adding new operations and associated equipment sets can increase the cost of fabrication, increase processing time, and reduce manufacturing throughput, it is also desired to implement a wafer surface treatment with a minimum of disruption to existing process flows.